The discussions about hardware will never be separated from the programming languages. This is used to control the hardware to fit the user’s goal. Effective and efficient logic algorithm is also needed to achieve perfect and quick work. Some times ago, the hardware controller that was often used was a microcontroller. Nowadays, with the increasingly widespread use of FPGAs, the programming language is also different from the microcontroller. FPGA can be programmed using Verilog or VHDL.
Many concepts and syntax are needed to understand how to design VHDL as a part of FPGA programming. In most cases, the decision to choose and use VHDL code rather than Verilog or SystemC code, depends on the choice of the designer itself and more on the availability of supporting software and company needs. For many years, there has been a long debate that has never ended between the VHDL users community and Verilog.
They argue about which code is the best to use and what code is more complete in terms of the rules of writing. Indeed, between the two codes has a significant difference. But philosophically, the basic difference from VHDL with Verilog is about the context of the two languages themselves. Verilog comes from the tradition of “bottom-up” which has often been used in the Integrated Circuit (IC) Industry in terms of IC basic design. While the VHDL code is developed more to the “top-down” perspective.
Of course, there are many general and broad differences in the current context. However, clearly the difference can be seen in the basic syntax and methods of the two codes. Furthermore, one important thing about the advantage of VHDL is its ability to use a combination of levels from models that have different architectures. However, in fact the Verilog code also have the same concept even though it only exists in a module. Nevertheless, that advantage explicitly defined in VHDL and practically used together by multi-design.
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